WM8768GEDSSLASHV datasheet(18/38 Pages) WOLFSON

18 / 38 page

WM8768

Production Data

PD Rev 4.3 July 2010

RIGHT JUSTIFIED MODE

In right justified mode, the LSB of DIN1/2/3/4 is sampled by the WM8768 on the rising edge of BCLK

preceding a LRCLK transition. LRCLK are high during the left samples and low during the right

samples (Figure 14).

Figure 14 Right Justified Mode Timing Diagram

I2S MODE

In I2S mode, the MSB of DIN1/2/3/4 is sampled by the WM8768 on the second rising edge of BCLK

following a LRCLK transition. LRCLK are low during the left samples and high during the right

samples.

Figure 15 I2S Mode Timing Diagram

DSP MODE A

In DSP mode A, the MSB of DAC channel 1 left data is sampled by the WM8768 on the second

rising edge on BCLK following a LRCLK rising edge. DAC channel 1 right and DAC channels 2/3/4

data follow DAC channel 1 left data (Figure 16).

Figure 16 DSP Mode A Timing Diagram – DAC data input

LEFT CHANNEL

RIGHT CHANNEL

LRCIN

BCKIN

DIN1/2/3/4

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

LEFT CHANNEL

RIGHT CHANNEL

LRCIN

BCKIN

DIN1/2/3/4

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

1 BCKIN

LRCIN

BCKIN

DIN1

Input Word Length (IWL)

1/fs

CHANNEL 1

LEFT

n-1

LSB

MSB

n-1

CHANNEL 1

RIGHT

CHANNEL 2

LEFT

n-1

CHANNEL 4

RIGHT

NO VALID DATA

1 BCKIN

WM8768GEDS/V Datasheet(PDF) 18 Page - Wolfson Microelectronics plc

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