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SPEAR1340 Datasheet(PDF) 184 Page - STMicroelectronics

No. de pieza SPEAR1340
Descripción Electrónicos  Dual-core Cortex A9 HMI embedded MPU
PDF  200 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPEAR1340 Datasheet(HTML) 184 Page - STMicroelectronics

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Timing characteristics
SPEAr1340
184/200
Doc ID 023063 Rev 4
Figure 46.
SPI master mode external timing waveform (SPH = 1, SPO = 1)
5.15.2
SPI slave mode timings
Table 98.
SPI master mode timing characteristics (clock phase bit SPH = 1, SPO=0)
Symbol
Parameters
Min
Max
Unit
TSU
Setup time, MISO (input) valid before
SSP_SCK (output) falling edge
17.8
ns
TH
Hold time, MISO (input) valid after SSP_SCK
(output) falling edge
0
TD1
Delay time, SSP_SS#n (output) falling edge to
first SSP_SCK (output) falling edge
TSSP_SCK-8
TSSP_SCK-2
ns
TD2
Delay time, SSP_SCK (output) rising edge to
MOSI (output) transition
-3.8
12.5
ns
TD3
Delay time, SSP_SCK (output) falling edge to
SSP_SS#n (output) rising edge
TSSP_SCK + 2 TSSP_SCK +8
Table 99.
SPI master mode timing characteristics (clock phase bit SPH = 1, SPO=1)
Symbol
Parameters
Min
Max
Unit
TSU
Setup time, MISO (input) valid before
SSP_SCK (output) rising edge
17
ns
TH
Hold time, MISO (input) valid after SSP_SCK
(output) rising edge
0
TD1
Delay time, SSP_SS#n (output) falling edge to
first SSP_SCK (output) rising edge
TSSP_SCK-8
TSSP_SCK-2
ns
TD2
Delay time, SSP_SCK (output) falling edge to
MOSI (output) transition
-4.64
12.4
ns
TD3
Delay time, SSP_SCK (output) rising edge to
SSP_SS#n (output) rising edge
TSSP_SCK + 2 TSSP_SCK +8
DATA
MSB IN
LSB IN
LSB OUT
DATA
MSB OUT
SSP_SS#n
SSP_SCK
(SPO=1)
SSP_MISO
(input)
SSP_MOSI
(output)
T
SU
T
H
T
D1
T
D2
T
D3



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