SPEAR1340 datasheet(156/200 Pages) STMICROELECTRONICS

No. de pieza	SPEAR1340

Descripción Electrónicos	Dual-core Cortex A9 HMI embedded MPU

PDF	200 Pages

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Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

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Timing characteristics

SPEAr1340

156/200

Doc ID 023063 Rev 4

5.5

CLCD timing characteristics

This section describes the timing characteristics for the LCD display controller which can

work on the clock rising edge or on the clock falling edge.

The timing characterization is performed assuming an output load capacitance of 10 pF on

all outputs and using PLL3 as the clock source for the timing extractions.

Figure 20.

CLCD timing waveform

LCD_DATA = LCD_R[0-7], LCD_XR[0-7], LCD_B[0-7], LCD_XB[0-7], LCD_G[0-7], LCD_XG[0-7].

Table 63.

CLCD timing characteristics

Symbol

Description

Min

Max

Unit

TCLK

LCD_PCLK clock period

6.5

–

TCLKhigh

LCD_PCLK pulse high

–

TCLKlow

LCD_PCLK pulse low

–

TD1

LCD_PCLK rising edge to LCD_DATA,

LCD_VSYNC, LCD_HSYNC LCD_DE output data

delay

0.9

5.6

TD2

LCD_PCLK falling edge to LCD_DATA,

LCD_VSYNC, LCD_HSYNC LCD_DE output data

delay

15.8

LCD_PCLK

(output)

LCD_DATA

(1)

LCD_VSYNC

LCD_HSYNC

LCD_DE

(with polarity

configured as

rising edge)

tCLKhigh

tCLKlow

td1

LCD_DATA

(1)

LCD_VSYNC

LCD_HSYNC

LCD_DE

(with polarity

configured as

falling edge)

td2

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