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ST10F280 Datasheet(PDF) 234 Page - STMicroelectronics

No. de pieza ST10F280
Descripción Electrónicos  16-bit MCU with MAC unit, 512 Kbyte Flash memory and 18 Kbyte RAM
PDF  239 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F280 Datasheet(HTML) 234 Page - STMicroelectronics

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Electrical characteristics
ST10F280
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Doc ID 8673 Rev. 3
Figure 92.
SSC slave timing
1.
The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
2.
The bit timing is repeated for all bits to be transmitted or received.
t
313
t
314
t
315
t
315
t
315
t
316
t
i
B
t
u
O
t
s
a
L
t
i
B
t
u
O
t
s
12nd Out Bit
t
310
t
312
t
311
1)
2)
t
317
2nd.In Bit
1st.In Bit
t
318
t
317
Last.In Bit
t
318
SCLK
MRST
MTSR
GAPGCFT00947



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