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ST10F280 Datasheet(PDF) 230 Page - STMicroelectronics

No. de pieza ST10F280
Descripción Electrónicos  16-bit MCU with MAC unit, 512 Kbyte Flash memory and 18 Kbyte RAM
PDF  239 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F280 Datasheet(HTML) 230 Page - STMicroelectronics

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Electrical characteristics
ST10F280
230/239
Doc ID 8673 Rev. 3
Figure 89.
External bus arbitration, releasing the bus
1.
The ST10F280 will complete the currently running bus cycle before granting bus access.
2.
This is the first possibility for BREQ to become active.
3.
The CS outputs will be resistive high (pull-up) after t64.
t64
CC CSx release (1)
–15
–
15
ns
t65
CC CSx drive
-4
15
-4
15
ns
t66
CC Other signals release(1)
–15
–
15
ns
t67
CC Other signals drive
-4
15
-4
15
ns
1.
Partially tested, guaranteed by design characterization
Table 51.
External bus arbitration (continued)
Symbol
Parameter
Maximum CPU Clock
= 40MHz
Variable CPU Clock
1/2 TCL = 1 to 40MHz
Min.
Max.
Min.
Max.
t61
t63
t66
1)
t64
1)
2)
t62
3)
CLKOUT
HOLD
HLDA
BREQ
Others
CSx
(P6.x)
GAPGCFT00943



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