Integrated Silicon Solution, Inc. — www.issi.com

13

Rev. D

06/21/2011

1

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5

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9

10

11

12

IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,

IS64WV12816DBLL/DBLS

-20 ns

-25 ns

-35 ns

-45ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WriteCycleTime

20

—

25

—

35

—

45

—

ns

CEtoWriteEnd

12

—

18

—

25

—

35

—

ns

AddressSetupTime

12

—

15

—

25

—

35

—

ns

toWriteEnd

AddressHoldfromWriteEnd

0

—

0

—

0

—

0

—

ns

AddressSetupTime

0

—

0

—

0

—

0

—

ns

LB,UBValidtoEndofWrite

12

—

18

—

30

—

35

—

ns

WEPulseWidth(OE=HIGH)

12

—

18

—

30

—

35

—

ns

WEPulseWidth(OE=LOW)

17

—

20

—

30

—

35

—

ns

DataSetuptoWriteEnd

9

—

12

—

15

—

20

—

ns

DataHoldfromWriteEnd

0

—

0

—

0

—

0

—

ns

WELOWtoHigh-ZOutput

—

9

—

12

—

20

—

20

ns

WEHIGHtoLow-ZOutput

3

—

5

—

5

—

5

—

ns

Notes:

1. Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of

CE LOW and UB or LB, and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to

the rising or falling edge of the signal that terminates the write.