SST48CF008 datasheet(21/60 Pages) SST

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Data Sheet

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SST48CF008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 / 256

S71125-03-000

9/01

375

2.3.12 True IDE Mode I/O Input (Read) Timing Specification

Note: The maximum load on -IOIS16 is 1 LSTTL with 50pF total load.

All AC specifications are guaranteed by design.

FIGURE

2-7: TRUE IDE MODE I/O READ TIMING DIAGRAM

TABLE

2-9: TRUE IDE MODE I/O READ TIMING DIAGRAM

Item

Symbol

IEEE Symbol

Min1

1. All times are in nanoseconds.

Max1

Data Delay after IORD

td(IORD)

tlGLQV

Data Hold following IORD

th(IORD)

tlGHQX

IORD Width Time

tw(IORD)

tlGLIGH

Address Setup before IORD

tsuA(IORD)

tAVIGL

Address Hold following IORD

thA(IORD)

tlGHAX

CE Setup before IORD

tsuCE(IORD)

tELIGL

CE Hold following IORD

thCE(IORD)

tlGHEH

IOIS16 Delay Falling from Address

tdfIOIS16(ADR)

tAVISL

IOIS16 Delay Rising from Address

tdrIOIS16(ADR)

tAVISH

T2-9.2 375

375 ILL2-7.0

-CE

tdrIOIS16(ADR)

tdfIOIS16(ADR)

thA(IORD)

thCE(IORD)

td(IORD)

th(IORD)

tsuA(IORD)

tsuCE(IORD)

tw(IORD)

-IORD

-IOIS16

Dout

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