Data Sheet

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM

ROM/RAM Combo

SST30VR021 / SST30VR022 / SST30VR023

11

©2001 Silicon Storage Technology, Inc.

S71135-02-000

4/01

380

PACKAGING DIAGRAMS

32.TSOP-WH-ILL.4

Note:

1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±.05) mm.

4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.

8.10

7.90

.270

.170

1.05

0.95

.50

BSC

0.15

0.05

12.50

12.30

Pin # 1 Identifier

14.20

13.80

0.70

0.50