XTNETA1622DW datasheet(3/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Terminal Functions

PCI-bus interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

PACK64

182

I/O

(3 state)

PCI acknowledge 64-bit transfer. PACK64 is driven by the current target indicating the ability to

support a 64-bit access. When acknowledging a 64-bit access, the assertion of PACK64 is

coincident with the assertion of PDEVSEL. If PACK64 is not asserted coincident with PDEVSEL,

the transaction defaults to 32 bit.

PAD31 − PAD0

119 − 121,

123 − 124,

126 − 127,

129,

133 − 134,

136 − 139,

141 − 142,

158 − 160,

162,

164 − 167,

171 − 173,

175 − 177,

179, 181

I/O

(3 state)

PCI address bus and data bus. PAD31 − PAD0 are multiplexed on the same PCI terminals.

During the first phase of the address phase of a transaction, PAD31 − PAD0 contain a 32-bit PHY

address. This phase is the clock cycle when PFRAME is asserted.

During the data phase, PAD7 − PAD0 contain the least significant byte and PAD31 − PAD24

contain the most significant byte. Write data is stable when PIRDY is asserted. Read data is

stable when PTRDY is asserted. Data is transferred during those clock cycles when both PIRDY

and PTRDY are asserted.

PAD63 − PAD32

191,

193 − 195,

197,

199 − 202,

204,

206 − 209,

211 − 212,

214 − 215,

217 − 220,

222,

224 − 227,

229,

231 − 233,

235

I/O

(3 state)

PCI address bus and data bus. PAD63 − PAD32 are multiplexed on the same PCI terminals.

During the first phase of the address phase of a transaction, PAD63 − PAD32 contain a 32-bit

PHY address. This phase is the clock cycle when PFRAME is asserted.

During the data phase, PAD39 − PAD32 contain the least significant byte and PAD63 − PAD56

contain the most significant byte. Write data is stable when PIRDY is asserted. Read data is

stable when PTRDY is asserted. Data is transferred during those clock cycles when both PIRDY

and PTRDY are asserted.

PCBE3 − PCBE0

130, 144,

156, 169

I/O

(3 state)

PCI-bus command and byte enable. PCBE3 − PCBE0 lines are multiplexed on the same PCI

terminals. During the address phase of a transaction, PCBE3 − PCBE0 lines define the bus

command. During the data phase, PCBE3 −PCBE 0 lines define which bytes are valid.

PCBE7 − PCBE4

184 − 185,

187 , 189

I/O

(3 state)

PCI-bus command and byte enable. PCBE7 − PCBE4 lines are multiplexed on the same PCI

terminals. During the address phase of a transaction, PCBE7 − PCBE4 lines define the bus

command. During the data phase, PCBE7 − PCBE4 lines define which bytes are valid.

PCLK

114

PCI clock. PCLK provides timing for all transactions on the PCI interface.

PDEVSEL

149

I/O

(3 state)

PCI device select. When actively driven, PDEVSEL indicates that the address of the driving

device is decoded as the target of the current access. As an input, PDEVSEL indicates whether

any device on the bus is selected.

PFRAME

145

I/O

(3 state)

PCI frame. PFRAME is driven by the current master to indicate the beginning and duration of an

access. PFRAME is asserted at the beginning of the bus transaction and remains asserted

during data transfer. When PFRAME is deasserted, the transaction is in the final data phase.

PGNT

116

PCI bus grant. PGNT indicates to the agent that the arbiter has granted access to the bus. PGNT

is a point-to-point signal and every master has its own.

XTNETA1622DW Datasheet(PDF) 3 Page - Texas Instruments

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