VSP01M02 datasheet(13/91 Pages) TI1

No. de pieza	VSP01M02

Descripción Electrónicos	CCD Analog Front-End with Timing Generator and Vertical Driver for Digital Cameras

PDF	91 Pages

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Fabricante Electrónico	TI1 [Texas Instruments]

Página de inicio	http://www.ti.com

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13 / 91 page

SLAVE MODE: VD, HD SPECIFICATIONS

VD, HD Detect

MCK

VDAfterHD

HDAfterVD

ODDHD-VD

ODDVD-HD

MCK

VDAfterHD

HDAfterVD

ODDHD-VD

ODDVD-HD

VSP01M01

VSP01M02

www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009

The odd field of the two-field CCD operation and the first field of the even field operation is detected by the VD

and HD phase. The delay limit of the VD and HD phase is specified in Figure 2 and Figure 3.

Figure 2. VD, HD Falling Edge Detect

Figure 3. VD, HD Rising Edge Detect

Table 3. Timing Characteristics for Figure 2 and Figure 3(1)

PARAMETER

MIN

TYP

MAX

UNIT

tVD

VD trail-to-trail

τ (MCK cycles)

tHD

HD trail-to-trail

τ (MCK cycles)

VD trail delay limit for ODD detect

tODD HD-VD

τ (MCK cycles)

(register setting 02Fh[2:0])

HD trail delay limit for ODD detect

tODD HD-VD

τ (MCK cycles)

(register setting 02Fh[5:3])

(1)

The VD, HD edge is detected by the rising edge of MCK.

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