AFE5808A datasheet(22/66 Pages) TI1

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AFE5808A

SLOS729B – OCTOBER 2011 – REVISED APRIL 2012

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TIMING CHARACTERISTICS

(1)

Typical values are at 25°C, AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, Differential clock, CLOAD =

5pF, RLOAD = 100 Ω, 14Bit, sample rate = 65MSPS, unless otherwise noted. Minimum and maximum values are across the

full temperature range TMIN = 0°C to TMAX = 85°C with AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Aperture delay

The delay in time between the rising edge of the input sampling

0.7

clock and the actual time at which the sampling occurs

Aperture delay

Across channels within the same device

±150

matching

Aperture jitter

450

Fs rms

ADC latency

Default, after reset, or / 0 x 2 [12] = 1, LOW_LATENCY = 1

11/8

Input

clock

cycles

tdelay

Data and frame clock

Input clock rising edge (zero cross) to frame clock rising edge (zero

5.4

delay

cross) minus 3/7 of the input clock period (T).

Δtdelay

Delay variation

At fixed supply and 20°C T difference. Device to device

–1

tRISE

Data rise time Data fall

Rise time measured from –100 mV to 100 mV Fall time measured

0.14

time

from 100 mV to –100 mV 10 MHz < fCLKIN < 65 MHz

tFALL

0.15

tFCLKRISE

Frame clock rise time

Rise time measured from –100mV to 100mV Fall time measured

0.14

Frame clock fall time

from 100 mV to –100 mV 10 MHz < fCLKIN < 65MHz

tFCLKFALL

0.15

Frame clock duty cycle

Zero crossing of the rising edge to zero crossing of the falling edge

tDCLKRISE

Bit clock rise time Bit

Rise time measured from –100mV to 100mV Fall time measured

0.13

clock fall time

from 100 mV to –100 mV 10 MHz < fCLKIN < 65MHz

tDCLKFALL

0.12

Bit clock duty cycle

Zero crossing of the rising edge to zero crossing of the falling edge

10 MHz < fCLKIN < 65 MHz

(1)

Timing parameters are ensured by design and characterization; not production tested.

OUTPUT INTERFACE TIMING

(1) (2) (3)

Setup Time (tsu), ns

Hold Time (th), ns

tPROG = (3/7)x T + tdelay, ns

(for output data and frame clock)

fCLKIN,

Input Clock

Input Clock Zero-Cross (rising edge)

Data Valid to Input Clock Zero-

Input Clock Zero-Crossing to Data

Frequency

to Frame Clock Zero-Cross (rising

Crossing

Invalid

edge)

MHz

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

65/14bit

0.24

0.37

0.24

0.38

12.5

50/14bit

0.41

0.54

0.46

0.57

13.9

14.4

40/14bit

0.55

0.70

0.61

0.73

16.7

30/14bit

0.87

1.10

0.94

1.1

18.5

19.5

20.1

20/14bit

1.30

1.56

1.46

1.6

25.7

26.7

27.3

(1)

FCLK timing is the same as for the output data lines. It has the same relation to DCLK as the data pins. Setup and hold are the same

for the data and the frame clock.

(2)

Data valid is logic HIGH = +100mV and logic LOW = -100mV

(3)

Timing parameters are ensured by design and characterization; not production tested.

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