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DAC712PLG4 Datasheet(PDF) 5 Page - Texas Instruments

No. de pieza DAC712PLG4
Descripción Electrónicos  16-BIT DIGITAL-TO-ANALOG CONVERTER with 16-Bit Bus Interface
PDF  23 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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DAC712PLG4 Datasheet(HTML) 5 Page - Texas Instruments

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ELECTRICAL CHARACTERISTICS: DAC712PK, UK, PL, UL
DAC712
www.ti.com ................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009
At TA = +25°C, +VCC = +12V and +15V, and –VCC = –12V and –15V, unless otherwise noted.
DAC712PK, UK
DAC712PL, UL(1)
TEST
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
INPUT
RESOLUTION
Resolution
16
Bits
DIGITAL INPUTS
Input Code
Binary Twos Complement
Logic Levels(2)
VIH
+2.0
+VCC – 1.4
V
VIL
0
+0.8
V
IIH (VI = +2.7V)
±10
µA
IIL (VI = +0.4V)
±10
µA
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error
±2
LSB
TMIN to TMAX
±2
LSB
Differential Linearity Error
±2
±1
LSB
TMIN to TMAX
±2
±1
LSB
Monotonicity Over Temperature
15
16
Bits
Gain Error(3)
±0.1
%
TMIN to TMAX
±0.15
±0.2
%
Bipolar Zero Error(3)
±0.1
% FSR(4)
±20
mV
TMIN to TMAX
±0.15
% FSR
±30
mV
±0.003
% FSR/% VCC
Power-Supply Sensitivity of Full-Scale
±30
ppm FSR/% VCC
DYNAMIC PERFORMANCE
Settling Time (to ±0.003%FSR, 5k
Ω || 500pF Load)(5)
20V Output Step
6
10
µs
1LSB Output Step(6)
4
µs
Output Slew Rate
10
V/
µs
Total Harmonic Distortion + Noise
0dB, 1001Hz, fS = 100kHz
0.005
%
–20dB, 1001Hz, fS = 100kHz
0.03
%
–60dB, 1001Hz, fS = 100kHz
3.0
%
SINAD
1001Hz, fS = 100kHz
87
dB
Digital Feedthrough(6)
2
nV-s
Digital-to-Analog Glitch Impulse(6)
15
nV-s
Output Noise Voltage (Includes Reference)
120
nV/
√Hz
(1)
Shaded cells indicate same specification as the DAC712PK, UK grade.
(2)
Digital inputs are TTL- and +5V CMOS-compatible over the specified temperature range.
(3)
Errors externally adjustable to zero.
(4)
FSR means Full-Scale Range. For example, for a ±10V output, FSR = 20V.
(5)
Maximum represents the 3
σ limit. Not 100% tested for this parameter.
(6)
For the worst-case code changes: FFFFh to 0000h and 0000h to FFFFh. These are binary twos complement (BTC) codes.
Copyright © 2000–2009, Texas Instruments Incorporated
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Product Folder Link(s): DAC712



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