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ADIS16480/PCBZ Datasheet(PDF) 15 Page - Analog Devices |
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ADIS16480/PCBZ Datasheet(HTML) 15 Page - Analog Devices |
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15 / 40 page ![]() Data Sheet ADIS16480 Rev. 0 | Page 15 of 40 Name R/W Flash PAGE_ID Address Default Register Description Format FIR_COEF_Axxx R/W Yes 0x05 0x00 to 0x7E N/A FIR Filter Bank A, Coefficients 0 through 59 Table 71 FIR_COEF_Axxx R/W Yes 0x06 0x00 to 0x7E N/A FIR Filter Bank A, Coefficients 60 through 119 Table 71 FIR_COEF_Bxxx R/W Yes 0x07 0x00 to 0x7E N/A FIR Filter Bank B, Coefficients 0 through 59 Table 72 FIR_COEF_Bxxx R/W Yes 0x08 0x00 to 0x7E N/A FIR Filter Bank B, Coefficients 60 through 119 Table 72 FIR_COEF_Cxxx R/W Yes 0x09 0x00 to 0x7E N/A FIR Filter Bank C, Coefficients 0 through 59 Table 73 FIR_COEF_Cxxx R/W Yes 0x0A 0x00 to 0x7E N/A FIR Filter Bank C, Coefficients 60 through 119 Table 73 FIR_COEF_Dxxx R/W Yes 0x0B 0x00 to 0x7E N/A FIR Filter Bank D, Coefficients 0 through 59 Table 74 FIR_COEF_Dxxx R/W Yes 0x0C 0x00 to 0x7E N/A FIR Filter Bank D, Coefficients 60 through 119 Table 74 1 The GPIO_CTRL[7:4] bits reflect the logic levels on the DIOx lines and do not have a default setting. |
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