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AD9557/PCBZ Datasheet(PDF) 47 Page - Analog Devices

No. de pieza AD9557/PCBZ
Descripción Electrónicos  Dual Input Multiservice
PDF  92 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
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AD9557/PCBZ Datasheet(HTML) 47 Page - Analog Devices

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Data Sheet
AD9557
Rev. A | Page 47 of 92
CS
SCLK
SDIO
tHIGH
tLOW
tCLK
tS
tDS
tDH
tC
BIT N
BIT N + 1
Figure 48. Serial Control Port Timing—Write
Table 28. Serial Control Port Timing
Parameter
Description
tDS
Setup time between data and the rising edge of SCLK
tDH
Hold time between data and the rising edge of SCLK
tCLK
Period of the clock
Setup time between the CS falling edge and the SCLK rising edge (start of the communication cycle)
tS
Setup time between the SCLK rising edge and CS rising edge (end of the communication cycle)
tC
tHIGH
Minimum period that SCLK should be in a logic high state
tLOW
Minimum period that SCLK should be in a logic low state
tDV
SCLK to valid SDIO and SDO (see Figure 46)



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