DC to DC Synchronous Converter Design

Abdus Sattar, IXYS Corporation

IXAN0068

5

Overview of Synchronous Converter Power Loss: [1]

The losses in the synchronous converter’s power switches can be defined by:

BD

Gate

SW

C

Total

P

P

P

P

P

+

+

+

=

(8)

and output capacitor’s ESR loss play significant role in the converter design.

MOSFET Q1 and Q2’s Power Loss: [1]

The conduction losses: (replace D to 1-D for Sync FET, Q2):

)

(

2

)

(

on

DS

O

C

R

D

I

P

•

=

(9)

The gate-charge losses:

s

g

GS

C

g

f

Q

V

P

•

•

=

−

(10)

The switching losses:

Figure 5: Transitions waveforms of MOSFET for inductive load

The switching loss is,

)

(

)

(

off

t

on

t

Switching

P

P

P

+

=

2

]

}

{

[

)

(

)

(

)

(

)

(

(max)

s

off

t

off

DS

on

t

on

DS

DS

f

t

I

t

I

V

•

•

+

•

=

(11)

MOSFET Body Diode Loss: [1]

The body diode loss is a function of dead time and in every switching cycle; there are two

dead-time intervals, td1 and td2. The dead-time is defined as the time required when both

the MOSFETs Q1 and Q2 are OFF in order to prevent shoot-through.