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R5F10RF8AFP Datasheet(PDF) 44 Page - Renesas Technology Corp

No. de pieza R5F10RF8AFP
Descripción Electrónicos  Integrated LCD controller/driver, True Low Power Platform (as low as 75 關A/MHz, and 0.64 關A for RTC LVD), 1.6 V to 5.5 V operation, 8 to 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Applications
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F10RF8AFP Datasheet(HTML) 44 Page - Renesas Technology Corp

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RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Page 44 of 73
R01DS0157EJ0001 Rev.0.01
2012.02.20
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(5) Communication at different potential (2.5 V, 3 V) (fMCK/2) (CSI mode) (master mode, SCKp... internal clock
output)
(TA =
−40 to +85°C, 2.7 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V
≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 k
Ω
200
Note 1
ns
SCKp cycle time
tKCY1
2.7 V
≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 k
Ω
300
Note 1
ns
4.0 V
≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 k
Ω
tKCY1/2
− 50
ns
SCKp high-level width
tKH1
2.7 V
≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 k
Ω
tKCY1/2
−
120
ns
4.0 V
≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 k
Ω
tKCY1/2
− 7
ns
SCKp low-level width
tKL1
2.7 V
≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 k
Ω
tKCY1/2
− 10
ns
4.0 V
≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 k
Ω
58
ns
SIp setup time
(to SCKp
↑) Note 2
tSIK1
2.7 V
≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 k
Ω
121
ns
4.0 V
≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 k
Ω
10
ns
SIp hold time
(from SCKp
↑) Note 2
tKSI1
2.7 V
≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 k
Ω
10
ns
4.0 V
≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 k
Ω
60
ns
Delay time from SCKp
↓ to
SOp output
Note 2
tKSO1
2.7 V
≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 k
Ω
130
ns
4.0 V
≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 k
Ω
23
ns
SIp setup time
(to SCKp
↓) Note 3
tSIK1
2.7 V
≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 k
Ω
33
ns
4.0 V
≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 k
Ω
10
ns
SIp hold time
(from SCKp
↓) Note 3
tKSI1
2.7 V
≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 k
Ω
10
ns
4.0 V
≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 k
Ω
10
ns
Delay time from SCKp
↑ to
SOp output
Note 3
tKSO1
2.7 V
≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 k
Ω
10
ns
(Note, Caution and Remark are listed on the next page.)



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