Technical Note

8/11

BD5650AFVM

www.rohm.com

2011.11 - Rev.B

© 2011 ROHM Co., Ltd. All rights reserved.

In case that over current reduces and ΔVS become under 73mV during CP charging, an electric charge in CP capacitance

discharge and CP voltage returns to 0V. When over current detect for the second time, start to charge.

Its discharging velocity is shown in expression (8).

）

･

（

・

Rdis

CP

t

-

Vcp0

Vcp

exp

)

t

(



(8)

Vcp0 means CP terminal voltage at discharge start, and Rdis is internal discharge resistance:900Ω(typ.).

If you don’t set up a delay time, you need that CP terminal is open or connects 10pF order of magnitude. In this case, when

IC detects surge current in an instant, normal working stops by protection. Consequently, you need to use this mode

considering a characteristics of module.

In addition, when you don’t use a function that IC detects over current, you need to short ICT terminal to VSE terminal and

pull down to GND by about 10kΩ in CP terminal.

Regarding board layout around CP capacitance, you pay attention that CP capacitance will not be in parallel with noisy

parts and lines wherever possible, and place to short pattern line as possible.

●

Internal equivalent circuit diagram

VCT(1PIN)

OCP(4PIN)

VSE(6PIN)

ICT(7PIN)

CP(8PIN)

OUT(3PIN)

OCP

Pow

VSE

ICT

Vref

CP

OUT

Pow