74LVC1G00

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© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 9 — 7 December 2011

13 of 17

NXP Semiconductors

74LVC1G00

Single 2-input NAND gate

Fig 14. Package outline SOT1202 (XSON6)

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

SOT1202

sot1202_po

10-04-02

10-04-06

Unit

mm

max

nom

min

0.35

0.04

1.05

1.00

0.95

1.05

1.00

0.95

0.55

0.35

0.40

0.35

0.32

Dimensions

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

XSON6: extremely thin small outline package; no leads;

6 terminals; body 1.0 x 1.0 x 0.35 mm

SOT1202

b

0.20

0.15

0.12

DE

e

L

0.35

0.30

0.27

0

0.5

1 mm

scale

terminal 1

index area

D

E

(4

e

L

b

123

6

5

4

(6

A