ICS9DB803DI datasheet(3/21 Pages) IDT

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IDTTM/ICSTM

Eight Output Differential Buffer for PCIe Gen 2

ICS9DB803DI

REV A

06/18/08

ICS9DB803DI

Eight Output Differential Buffer for PCIe for Gen 2

Pin Description for OE_INV = 0

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

1SRC_DIV#

Active low Input for determining SRC output frequency SRC or SRC/2.

0 = SRC/2, 1= SRC

VDD

PWR

Power supply, nominal 3.3V

GND

PWR

Ground pin.

SRC_IN

0.7 V Differential SRC TRUE input

SRC_IN#

0.7 V Differential SRC COMPLEMENTARY input

6OE_0

Active high input for enabling output 0.

0 = tri-state outputs, 1= enable outputs

7OE_3

Active high input for enabling output 3.

0 = tri-state outputs, 1= enable outputs

DIF_0

OUT

0.7V differential true clock output

DIF_0#

OUT

0.7V differential complement clock output

GND

PWR

Ground pin.

VDD

PWR

Power supply, nominal 3.3V

DIF_1

OUT

0.7V differential true clock output

DIF_1#

OUT

0.7V differential complement clock output

OE_1

Active high input for enabling output 1.

0 = tri-state outputs, 1= enable outputs

OE_2

Active high input for enabling output 2.

0 = tri-state outputs, 1= enable outputs

DIF_2

OUT

0.7V differential true clock output

DIF_2#

OUT

0.7V differential complement clock output

GND

PWR

Ground pin.

VDD

PWR

Power supply, nominal 3.3V

DIF_3

OUT

0.7V differential true clock output

DIF_3#

OUT

0.7V differential complement clock output

BYPASS#/PLL

Input to select Bypass(fan-out) or PLL (ZDB) mode

0 = Bypass mode, 1= PLL mode

SCLK

Clock pin of SMBus circuitry, 5V tolerant.

SDATA

I/O

Data pin for SMBus circuitry, 5V tolerant.

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