LC87F76C8A

No.A0858-15/24

Continued from preceding page.

Specification

Parameter

Symbol

Pin/Remarks

Conditions

VDD[V]

min

typ

max

unit

Rpu(1)

4.5 to 5.5

15

35

80

Pull-up MOS Tr.

resistance

Rpu(2)

• Ports 0, 1, 3, 7

• Ports A, B, C, D

VOH=0-9VDD

2.2 to 4.5

18

50

150

k

Ω

VHYS(1)

• Ports 1, 7

• RES

2.2 to 5.5

0.1VDD

Hysteresis voltage

VHYS(2)

Port 87 small signal

input side

2.2 to 5.5

0.1VDD

V

Pin capacitance

CP

All pins

• VIN=VSS for pins other than

that under test

• f=1MHz

• Ta=25

°C

2.2 to 5.5

10

pF

Input sensitivity

Vsen

Port 87 small signal

input side

2.2 to 5.5

0.12VDD

Vp-p

Serial I/O Characteristics at Ta = -20°C to +85°C, VSS1 = VSS2 = VSS3 = 0V

1. SIO0 Serial I/O Characteristics (Note 4-1-1)

Specification

Parameter

Symbol

Pin/Remarks

Conditions

VDD[V]

min

typ

max

unit

Frequency

tSCK(1)

2

Low level

pulse width

tSCKL(1)

1

tSCKH(1)

See Fig. 6.

1

High level

pulse width

tSCKHA(1)

SCK0(P12)

• Continuous data

transmission/reception mode

• See Fig. 6.

• (Note 4-1-2)

2.2 to 5.5

4

Frequency

tSCK(2)

4/3

tCYC

Low level

pulse width

tSCKL(2)

1/2

tSCKH(2)

• CMOS output selected

• See Fig. 6.

1/2

tSCK

High level

pulse width

tSCKHA(2)

SCK0(P12)

• Continuous data

transmission/reception mode

• CMOS output selected

• See Fig. 6.

2.2 to 5.5

tSCKH(2)

+2tCYC

tSCKH(2)

+(10/3)

tCYC

tCYC

Data setup time

tsDI(1)

0.03

Data hold time

thDI(1)

SB0(P11),

SI0(P11)

• Must be specified with

respect to rising edge of

SIOCLK

• See Fig. 6.

2.2 to 5.5

0.03

tdDO(1)

• Continuous data

transmission/reception mode

• (Note 4-1-3)

(1/3)tCYC

+0.05

tdDO(2)

• Synchronous 8-bit mode

• (Note 4-1-3)

1tCYC

+0.05

Output delay

time

tdDO(3)

SO0(P10),

SB0(P11)

(Note 4-1-3)

2.2 to 5.5

(1/3)tCYC

+0.05

μs

Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.

Note 4-1-2: To use serial-clock-input in continuous transmission/reception mode, a time from SI0RUN being set when

serial clock is "H" to the first falling edge of the serial clock must be longer than tSCKHA.

Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning

of output state change in open drain output mode. See Fig. 6.