GS9025ACTME3 datasheet(13/18 Pages) GENNUM

13 / 18 page

GENNUM CORPORATION

522 - 75 - 05

13 of 18

2.5.1 Lock Time

The lock time of the GS9025A depends on whether the

input data is switching synchronously or asynchronously.

Synchronous switching means that the input data is

changed from one source to another source which is at the

same data rate (but different phase). Asynchronous

switching means that the input data is changed from one

source to another source which is at a different data rate.

When input data to the GS9025A is removed, the GS9025A

latches the current state of the counter (divider modulus).

Therefore, when data is reapplied, the GS9025A begins the

lock procedure at the previous locked data rate. As a result,

in synchronous switching applications, the GS9025A locks

very quickly. The nominal lock time depends on the

switching time and is summarized in Table 4.

In asynchronous switching applications, including power

up, the lock time is determined by the frequency acquisition

circuit (see section 2.2, Frequency Acquisition).

To acquire lock in manual mode, the frequency acquisition

circuit may have to sweep over an entire cycle depending

on initial conditions. Maximum lock time is 2Tcycle + 2tsys.

To acquire lock in auto tune mode, the frequency

acquisition circuit may have to cycle through 5 possible

counter states depending on initial conditions. Maximum

lock time is 6Tcycle + 2tsys.

The nominal value of Tcycle for the GS9025A operating in a

typical SMPTE 259M application is approximately 1.3ms.

The GS9025A has a dedicated LOCK output (pin 39)

indicating when the device is locked.

NOTE: In synchronous switching applications where the

switching time is less than 0.5µs, the LOCK output will NOT

be de-asserted and the data outputs will NOT be muted.

2.5.2 DVB-ASI

Design Note: For DVB-ASI applications having significant

instances of few bit transitions or when only K28.5 idle bits

are transmitted, the wide-band PLL in the GS9025A may

lock at 243MHz being the first 27MHz sideband below

270MHz. In this case, when normal bit density signals are

transmitted, the PLL will correctly lock onto the proper

270MHz carrier.

2.6 Output Data Muting

The GS9025A internally mutes the SDO and SDO outputs

when the device is not locked. When muted, SDO/SDO are

latched providing a logic state to the subsequent circuit

and avoiding a condition where noise could be amplified

and appear as data.

The output data muting timing is shown in Figure 21.

Fig. 21 Output Data Muting Timing

2.7 Clock Enable

When CLK_EN is high, the GS9025A SCO/SCO outputs are

enabled. When CLK_EN is low, the SCO/SCO outputs are

set to a high Z state and float to VCC. Disabling the clock

outputs

results

power

savings

10%.

recommended that the CLK_EN input be hard wired to the

desired state. For applications which do not require the

clock output, connect CLK_EN to ground and connect the

SCO/SCO outputs to VCC.

2.8 Stressful Data Patterns

All PLL's are susceptible to stressful data patterns which

can introduce bit errors in the data stream. PLL's are most

sensitive to patterns which have long run lengths of 0's or

1's (low data transition densities for a long period of time).

The GS9025A is designed to operate with low data

transition densities such as the SMPTE 259M pathological

signal (data transition density = 0.05).

2.9 PLL Design Guidelines

The reclocking performance of the GS9025A is primarily

determined by the PLL. Thus, it is important that the system

designer is familiar with the basic PLL design equations.

A model of the GS9025A PLL is shown in Figure 22. The

main components are the phase detector, the VCO, and the

external loop filter components.

TABLE 4.

SWITCHING TIME

LOCK TIME

<0.5µs

10µs

0.5µs - 10ms

2tsys

>10ms

2Tcycle + 2tsys

LOCK

DDI

SDO

VALID

DATA

NO DATA TRANSITIONS

VALID

DATA

OUTPUTS MUTED

GS9025ACTME3 Datasheet(PDF) 13 Page - Gennum Corporation

GS9025ACTME3 Datasheet(HTML) 13 Page - Gennum Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datasheet Descarga

Enlace URL