Philips Semiconductors

PCF85103C-2

256

Product data

Rev. 04 — 22 October 2004

8 of 20

9397 750 14218

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

initiated in the same manner as the byte write operation. The master can transit eight

data bytes within one transmission. After receipt of each byte, the PCF85103C-2 will

respond with an acknowledge. The typical E/W time in this mode is

9

× 3.5 ms = 31.5 ms. Erasing a block of 8 bytes in page mode takes typical 3.5 ms

and sequential writing of these 8 bytes another typical 28 ms.

After the receipt of each data byte, the three low-order bits of the word address are

internally incremented. The high-order five bits of the address remain unchanged.

data transfer is terminated by the master after the 8th byte with a STOP condition. If

the master transmits more than eight bytes prior to generating the STOP condition,

no acknowledge will be given on the ninth (and following) data bytes and the whole

transmission will be ignored and no programming will be done. As in the byte write

operation, all inputs are disabled until completion of the internal write cycles.

Fig 5.

Auto-increment memory word address; two byte write.

S

0A

SLAVE ADDRESS

WORD ADDRESS

AA

DATA

P

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

A

DATA

R/W

auto increment

word address

auto increment

word address

MBA701

Fig 6.

Page write operation; eight bytes.

S0 A

SLAVE ADDRESS

WORD ADDRESS

A

A

DATA N

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

R/W

auto increment

word address

acknowledge

from slave

A

DATA N + 1

auto increment

word address

002aaa245

A

acknowledge

from slave

A

DATA N + 7

auto increment

word address

last byte