CY8C21634B datasheet(4/47 Pages) CYPRESS

4 / 47 page

CY8C21634B, CY8C21534B, CY8C21434B

CY8C21334B, CY8C21234B

Document Number: 001-67345 Rev. *A

Page 4 of 47

The Analog System

The analog system consists of four configurable blocks that allow

for the creation of complex analog signal flows. Analog

peripherals are very flexible and can be customized to support

specific application requirements. Some of the common PSoC

analog functions for this device (most available as user modules)

are:

■ ADCs (single or dual, with 8-bit or 10-bit resolution)

■ Pin-to-pin comparator

■ Single-ended comparators (up to two) with absolute (1.3 V)

reference or 8-bit DAC reference

■ 1.3-V reference (as a system resource)

In most PSoC devices, analog blocks are provided in columns of

three, which includes one continuous time (CT) and two switched

capacitor (SC) blocks. The CY8C21x34B devices provide limited

functionality Type E analog blocks. Each column contains one

CT Type E block and one SC Type E block. Refer to the PSoC

Technical Reference Manual for detailed information on the

CY8C21x34B’s Type E analog blocks.

Figure 2. Analog System Block Diagram

The Analog Multiplexer System

The analog mux bus can connect to every GPIO pin. Pins may

be connected to the bus individually or in any combination. The

bus also connects to the analog system for analysis with

comparators and analog-to-digital converters. An additional 8:1

analog input multiplexer provides a second path to bring Port 0

pins to the analog array.

Switch-control logic enables selected pins to precharge

continuously under hardware control. This enables capacitive

measurement for applications such as touch sensing. Other

multiplexer applications include:

■ Track pad, finger sensing

■ Chip-wide mux that allows analog input from any I/O pin

■ Crosspoint connection between any I/O pin combinations

Additional System Resources

System resources, some of which are listed in the previous

sections, provide additional capability useful to complete

systems. Additional resources include a switch-mode pump,

low-voltage detection, and power-on-reset (POR).

■ Digital clock dividers provide three customizable clock

frequencies for use in applications. The clocks may be routed

to both the digital and analog systems. Additional clocks can

be generated using digital PSoC blocks as clock dividers.

■ The I

2C module provides 100- and 400-kHz communication

over two wires. Slave, master, and multi-master modes are all

supported.

■ LVD interrupts can signal the application of falling voltage

levels, while the advanced POR circuit eliminates the need for

a system supervisor.

■ An internal 1.3-V reference provides an absolute reference for

the analog system, including ADCs and DACs.

■ An integrated switch-mode pump generates normal operating

voltages from a single 1.2-V battery cell, providing a low cost

boost converter.

■ Versatile analog multiplexer system.

ACOL1MUX

ACE00

ACE01

Array

Array Input

Configuration

ASE10

ASE11

Analog Mux Bus

All I/O

ACI0[1:0]

ACI1[1:0]

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