TLE6368 datasheet(13/59 Pages) INFINEON

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TLE 6368 / SONIC

Data Sheet

Rev. 2.2, 2006-12-01

Q_LDO1 had decreased below 3.3V (max.), the SPI will reset to the default settings

including the 8ms delay time. If the voltage on Q_LDO1 during sleep or power off mode

was kept above 3.3V the delay time set by the last SPI command is valid.

Figure 5 Undervoltage reset timing

2.7

RAM good flag

A RAM good flag will be set within the SPI status word when the Q_LDO1 voltage drops

below 2.3V. A second one will be set if Q_LDO2 drops below typical 1.4V. Both RAM

good flags can be read after power up to determine if a cold or warm start needs to be

processed. Both RAM good flags will be reset after each SPI cycle.

2.8

ERR Pin

A hardware error pin indicates any fault conditions on the chip. It should be connected to

an interrupt input of the microcontroller. A low signal indicates an error condition. The

microcontroller can read the root cause of the error by reading the SPI register.

2.9

Window Watchdog

The on board window watchdog for supervision of the µC works in combination with the

SPI. The window watchdog logic is turned off per default and can be activated by one

special bit combination in the SPI command word. When operating, the window

watchdog is triggered when CS is low and Bit WD-Trig in the SPI command word is set

to “1”. The watchdog trigger is recognized with the low to high transition of the CS signal.

To allow reading the SPI at any time without getting a reset due to misinterpretation the

WD-Trig bit has to be set to “0” to avoid false trigger conditions.

FB/L_IN

Q_LDOx

RTH,Q_LDOx

RES

< t

thermal

shutdown

under

voltage

over

load

RES

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