Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Spanish  ▼
ALLDATASHEET.ES

X  

Preview PDF HTML

MPC8306EC Datasheet(PDF) 64 Page - Freescale Semiconductor, Inc

No. de pieza MPC8306EC
Descripción Electrónicos  PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications
PDF  76 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8306EC Datasheet(HTML) 64 Page - Freescale Semiconductor, Inc

Back Button MPC8306EC Datasheet HTML 60Page - Freescale Semiconductor, Inc MPC8306EC Datasheet HTML 61Page - Freescale Semiconductor, Inc MPC8306EC Datasheet HTML 62Page - Freescale Semiconductor, Inc MPC8306EC Datasheet HTML 63Page - Freescale Semiconductor, Inc MPC8306EC Datasheet HTML 64Page - Freescale Semiconductor, Inc MPC8306EC Datasheet HTML 65Page - Freescale Semiconductor, Inc MPC8306EC Datasheet HTML 66Page - Freescale Semiconductor, Inc MPC8306EC Datasheet HTML 67Page - Freescale Semiconductor, Inc MPC8306EC Datasheet HTML 68Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 64 / 76 page
background image
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
64
Freescale Semiconductor
Clocking
NOTE
Core VCO frequency = core frequency
 VCO divider. The VCO divider
(RCWL[COREPLL[0:1]]), must be set properly so that the core VCO
frequency is in the range of 400–800 MHz.
22.4
QUICC Engine PLL Configuration
The QUICC Engine PLL is controlled by the RCWL[CEPMF] and RCWL[CEPDF] parameters. Table 58
shows the multiplication factor encodings for the QUICC Engine PLL.
10
0001
0
1:1
8
11
0001
0
1:1
8
00
0001
1
1.5:1
 2
01
0001
1
1.5:1
 4
10
0001
1
1.5:1
 8
11
0001
1
1.5:1
 8
00
0010
0
2:1
 2
01
0010
0
2:1
 4
10
0010
0
2:1
 8
11
0010
0
2:1
 8
00
0010
1
2.5:1
 2
01
0010
1
2.5:1
 4
10
0010
1
2.5:1
 8
11
0010
1
2.5:1
 8
00
0011
0
3:1
 2
01
0011
0
3:1
 4
10
0011
0
3:1
 8
11
0011
0
3:1
 8
Table 58. QUICC Engine PLL Multiplication Factors
RCWL[CEPMF]
RCWL[CEPDF]
QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/
(1 + RCWL[CEPDF)
00000–00001
0
Reserved
00010
0
 2
00011
0
 3
00100
0
 4
Table 57. e300 Core PLL Configuration (continued)
RCWL[COREPLL]
core_clk : csb_clk Ratio
VCO Divider
0-1
2-5
6



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76


Datasheet Descarga

Go To PDF Page


Enlace URL



¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Enlace a la hoja de datos    |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com