3

Pin Number Function

FX802

J

15

16

17

18

19

20

21

22

23

24

25

26

27

28

FX802

LG/LS

13

14

15

16

17

18

19

20

21

22

23

24

DRAM Data In/A0/ (Direct Access – Encoder Out (ENO)): Connected to the DRAM data input and

address line A0. With no DRAM employed this output is available (in Direct Access mode) as the Delta

Encoder digital data output. Direct Access control is achieved by Control Register byte 1 – bit 6.

DRAM Data Out/ A1/ (Direct Access – Decoder In (DEI)): Connected to the DRAM data output and

address line A1. With no DRAM employed this pin is available (in Direct Access mode) as the Delta

Decoder digital data input. Direct Access control is achieved by Control Register byte 1 – bit 6.

DRAM A2/ (Direct Access – Decoder Clock (DCK)): DRAM address line A2. With no DRAM

employed this pin is available (in Direct Access mode) as the Delta Decoder Clock input. Direct Access

control is achieved by Control Register byte 1 – bit 6.

DRAM A3/ (Direct Access – Encoder Clock (ECK)): DRAM address line A3. With no DRAM

employed this pin is available (in Direct Access mode) as the Delta Encoder Clock output. Direct

Access control is achieved by Control Register byte 1 – bit 6.

DRAM A4:

DRAM address line A4.

DRAM A5:

DRAM address line A5.

DRAM A6:

DRAM address line A6.

DRAM A7:

DRAM address line A7.

DRAM A8:

DRAM address line A8.

Row Address Strobe 4 (RAS4): Should be connected to the Row Address Strobe input of the fourth

1Mbit DRAM chip (if fitted).

Row Address Strobe 3 (RAS3): Should be connected to the Row Address Strobe input of the third

1Mbit DRAM chip (if fitted).

DRAM A9:

DRAM address line A9. This pin is not connected when a 256kbit DRAM is employed.

Note: To simplify PCB layout, the DRAM address inputs A0 – A8 may be connected in any physical

order to the DVSR Codec output pins A0 – A8.

Column Address Strobe (CAS): The DRAM Column Address Strobe pin. Should be connected to the

CAS pins of all DRAM chips.

V

Positive supply rail. A single, stable +5-volt supply is required. Levels and voltages within the

DVSR Codec are dependant upon this supply.