5

Application Information ......

FX489

GMSK MODEM

Rx

CIRCUITS

Tx

CIRCUITS

Rx DATA

Rx CLOCK

Tx DATA

Tx CLOCK

Tx OUT

SIGNAL AND

DC LEVEL

ADJUSTMENT

SIGNAL AND

DC LEVEL

ADJUSTMENT

Rx SIGNAL IN

Rx FEEDBACK

Rx FREQUENCY

DISCRIMINATOR

RxD

RxC

TxD

TxC

MICRO

CONTROLLER

FREQUENCY

MODULATOR

Fig.3 External Signal Paths

MICROCONTROLLER

SERIAL

I/O PORT

RxD

RxC

TxD

TxC

V

DD

SETTINGS: D/Rate 4800bps - BT 0.5 - Rx & Tx Enabled

4.9152MHz

XTAL/CLOCK

Tx ENABLE

ClkDIVA

ClkDIVB

BT

Tx PS

Rx PS

Rx S/N

FX489

GMSK MODEM

PLLacq

RxDCacq

XTAL

Rx DATA

Rx CLOCK

Tx DATA

Tx CLOCK

RxHOLD

Clock Oscillator and Dividers

The Tx and (nominal) Rx data rates are determined

by division of the frequency present at the Xtal pin,

which may be generated by the on-chip Xtal oscillator

or be derived from an external source.

The division ratio is controlled by the logic level

inputs on the ClkDivA/B pins, and is shown in the table

below - together with an indication of how various

‘standard’ data rates may be derived from common µP

Xtal frequencies.

Xtal/Clock Frequency (MHz)

4.096

4.9152

2.048

2.4576

[12.288/3]

[6.144/3]

[12.288/5]

Division ratio

ClkDiv ClkDiv

Xtal Freq/

Data Rate (bps)

A

B

Data Rate

0

0

128

16000

19200

0

1

256

16000

19200

8000

9600

1

0

512

8000

9600

4000

4800

1

1

1024

4000

4800

Note

that device operation is not

guaranteed or specified above 19,200 bits/s

or below 4,000 bits/s.

Table 1 Clock/Data Rates

Radio Channel Requirements

To achieve legal adjacent channel performance at

high bit-rates, a radio with an accurate carrier

frequency and an accurate modulation index will be

required.

To achieve optimum channel utilization, (eg. low

BER and high data-rates) attention must be paid to the

phase and frequency response of both the IF and

baseband circuitry.

Fig.4 Minimum µController System Connections