ADSP-BF504 datasheet(40/80 Pages) AD

No. de pieza	ADSP-BF504

Descripción Electrónicos	Blackfin Embedded Processor

PDF	80 Pages

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Fabricante Electrónico	AD [Analog Devices]

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40 / 80 page

Rev. PrC

Page 40 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

Table 31. Serial Ports — External Late Frame Sync

Parameter

DDEXT=1.8 V

DDEXT=2.5/3.3 V

Min

Max

Min

Max

Unit

Switching Characteristics

tDDTLFSE

Data Delay from Late External TFSx

or External RFSx in Multi-channel Mode With MFD = 0

1, 2

11.2

10.0

tDTENLFSE

Data Enable from External RFSx in Multi-channel Mode With

MFD = 01, 2

0.0

1 When in multi-channel mode, TFSx enable and TFSx valid follow t

DTENLFSE and tDDTLFSE.

2 If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2 then tDDTTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFSE apply.

Figure 20. Serial Ports — External Late Frame Sync

RSCLKx

RFSx

DTx

DRIVE

SAMPLE

EXTERNAL RFSx IN MULTI-CHANNEL MODE WITH MCE = 1

1ST BIT

tHOFSE/I

tDTENLFSE

tDDTLFSE

tSFSE/I

TSCLKx

TFSx

DTx

DRIVE

SAMPLE

LATE EXTERNAL TFSx

1ST BIT

tHOFSE/I

tDDTLFSE

tSFSE/I

ADSP-BF504 Datasheet(PDF) 40 Page - Analog Devices

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