ADSP-21469KBZ-ENG2 datasheet(39/56 Pages) AD

No. de pieza	ADSP-21469KBZ-ENG2

Descripción Electrónicos	SHARC Processor material that is subject to change without notice

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ADSP-21469/ADSP-21469W

Preliminary Technical Data

Rev. PrB

Page 39 of 56

November 2008

Sample Rate Converter—Serial Output Port

For the serial output port, the frame-sync is an input and it

should meet setup and hold times with regard to SCLK on the

output port. The serial data output, SDATA, has a hold time

and delay specification with regard to SCLK. Note that SCLK

rising edge is the sampling edge and the falling edge is the

drive edge.

Table 36. ASRC, Serial Output Port

Parameter

Min

Max

Unit

Timing Requirements

tSRCSFS

FS Setup Before SCLK Rising Edge

TBD

tSRCHFS

FS Hold After SCLK Rising Edge

TBD

tSRCCLKW

Clock Width

TBD

tSRCCLK

Clock Period

TBD

Switching Characteristics

TBD

tSRCTDD

Transmit Data Delay After SCLK Falling Edge

TBD

tSRCTDH

Transmit Data Hold After SCLK Falling Edge

TBD

1 AMI_DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

Figure 26. ASRC Serial Output Port Timing

DAI_P20

-1

(SCLK)

DAI_P20

-1

(FS)

tSRCSFS

tSRCHFS

DAI_P20

-1

(SDATA)

tSRCTDD

tSRCTDH

SAMPLE EDGE

tSRCCLK

tSRCCLKW

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