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MPC8572ECLPXAVND Datasheet(PDF) 65 Page - Freescale Semiconductor, Inc |
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MPC8572ECLPXAVND Datasheet(HTML) 65 Page - Freescale Semiconductor, Inc |
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65 / 140 page  MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 65 Programmable Interrupt Controller 11 Programmable Interrupt Controller In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed polarity), it must remain asserted for at least 3 system clocks (SYSCLK periods). 12 JTAG This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8572E. Table 52 provides the JTAG AC timing specifications as defined in Figure 37 through Figure 39. Table 52. JTAG AC Timing Specifications (Independent of SYSCLK) 1 At recommended operating conditions with OVDD of 3.3 V ± 5%. Parameter Symbol 2 Min Max Unit Notes JTAG external clock frequency of operation fJTG 0 33.3 MHz — JTAG external clock cycle time t JTG 30 — ns — JTAG external clock pulse width measured at 1.4 V tJTKHKL 15 — ns — JTAG external clock rise and fall times tJTGR & tJTGF 02 ns 6 TRST assert time tTRST 25 — ns 3 Input setup times: Boundary-scan data TMS, TDI tJTDVKH tJTIVKH 4 0 — — ns 4 Input hold times: Boundary-scan data TMS, TDI tJTDXKH tJTIXKH 20 25 — — ns 4 Valid times: Boundary-scan data TDO tJTKLDV tJTKLOV 4 4 20 25 ns 5 Output hold times: Boundary-scan data TDO tJTKLDX tJTKLOX 30 30 — — ns 5 |
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