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TLE6220GP Datasheet(PDF) 10 Page - Infineon Technologies AG

No. de pieza TLE6220GP
Descripción Electrónicos  Smart Quad Low-Side Switch Short Circuit Protection
PDF  19 Pages
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Fabricante Electrónico  INFINEON [Infineon Technologies AG]
Página de inicio  http://www.infineon.com
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TLE6220GP Datasheet(HTML) 10 Page - Infineon Technologies AG

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Data Sheet TLE 6220 GP
V2.1
Page
2007-05-03
10
If the OR operation is programmed it is latched until it is overwritten by the AND operation.
5. HHHH DDDD
- AND operation, and ‘full diagnosis’
With HHHH as the control word, each of the input signals IN1...IN4 are 'AND'ed with the corre-
sponding data bits (DDDD).
&
Output
Driver
IN 1...4
Serial Input,
data bits 0...3
The AND operation implies that the output can be switched off by the SPI data bit input, even if
the corresponding parallel input is in the ON state.
⇒ SPI Priority for OFF-state
This also implies that the serial input data bit can only switch the output channel ON if the cor-
responding parallel input is in the ON state.
If the AND operation is programmed it is latched until it is overwritten by the OR operation.
Control words beside No. 1- 5
All control words except those for Diag Only, Read Back of Inputs, SPI echo, will be accepted as
an OR or an AND command with valid data bits depending on the boolean operation which was
programmed before.
Example 1:
LLHH HLLH: OR operation between parallel inputs and data bits, i.e channel 1 and 4 will be
switched on.
The next command is now: LHHH HHLH
LHHH as command word has no special meaning but it will be accepted as an OR operation and
the data bits will be ORed with the inputs and the outputs 1,3 and 4 will be switched on.
See above: 'If the OR operation is programmed it is latched until it is overwritten by the AND
operation.'
Example 2:
HHHH LLHL means: Data bits will be ANDed with the parallel inputs and the outputs switch ac-
cordingly. Then HLLH HHLH is clocked in: AND was latched by the command before and is now
valid again by using the HLLH command word. So the data bits will be accepted and again
ANDed with the parallel input signals.
See above: 'If the AND operation is programmed it is latched until it is overwritten by the OR
operation.'



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