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L9803 Datasheet(PDF) 27 Page - STMicroelectronics

No. de pieza L9803
Descripción Electrónicos  Super smart power motor driver with 8-Bit MCU, RAM, EEPROM, ADC, WDG, Timers, PWM and H-bridge driver
PDF  126 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L9803 Datasheet(HTML) 27 Page - STMicroelectronics

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L9803
Clocks, Reset, Interrupts & Power saving modes
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3.6
Interrupts
A list of interrupt sources is given in Table 4 below, together with relevant details for each
source. Interrupts are serviced according to their order of priority, starting with I0, which has
the highest priority, and so to I12, which has the lowest priority.
The following list describes the origins for each interrupt level:
–
I0 connected to Ports PA0-PA7, PB0-PB1
–
I1 connected to CAN
–
I2 connected to Power Diagnostics
–
I3 connected to Output Compare of Timer 1
–
I4 connected to Input Capture of TImer 1
–
I5 connected to Timer 1 Overflow
–
I6 connected to Output Compare of Timer 2
–
I7 connected to Input Capture of TImer 2
–
I8 connected to Timer 2 Overflow
–
I9 connected to ADC End Of Conversion
–
I10 connected to PWM 1 Overflow
–
I11 connected to PWM 2 Overflow
–
I12 connected to EEPROM
Exit from Halt mode may only be triggered by an External Interrupt on one of the following
ports: PA0-PA7 (I0), PB0-PB1 (I0), or by an Internal Interrupt coming from CAN peripheral
(I1).
If more than one input pin of a group connected to the same interrupt line are selected
simultaneously, the OR of this signals generates the interrupt.
Table 4.
Interrupt Mapping
Interrupts
Register
Flag name
Interrupt
source
Vector
Address
Reset
N/A
N/A
-
FFFEh-FFFFh
Software
N/A
N/A
-
FFFCh-FFFDh
Ext. Interrupt (Ports PA0-PA7, PB0-
PB1)
N/A
N/A
I0
FFFAh-FFFBh
Receive Interrupt Flag
CAN Status
RXIFi
I1
FFF8h-FFF9h
Transmit Interrupt Flag
TXIF
Error Interrupt Pending
EPND
Power Bridge Short Circuit
Bridge Control
Status
SC
I2
FFF6h-FFF7h
Overtemperature
OVT
Output Compare 1
Timer 1 Status
OCF1_1
I3
FFF4h-FFF5h
Output Compare 2
OCF2_1
Input Capture 1
Timer 1 Status
ICF1_1
I4
FFF2h-FFF3h
Input Capture 2
ICF2_1



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