82G33 datasheet(6/437 Pages) INTEL

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Datasheet

5.2.22

C1CYCTRKPCHG—Channel 1 CYCTRK PCHG............................... 146

5.2.23

C1CYCTRKACT—Channel 1 CYCTRK ACT ................................... 147

5.2.24

C1CYCTRKWR—Channel 1 CYCTRK WR ..................................... 148

5.2.25

C1CYCTRKRD—Channel 1 CYCTRK READ................................... 149

5.2.26

C1CKECTRL—Channel 1 CKE Control ........................................ 150

5.2.27

C1REFRCTRL—Channel 1 DRAM Refresh Control......................... 151

5.2.28

C1ODTCTRL—Channel 1 ODT Control ....................................... 153

5.2.29

EPC0DRB0—ME Channel 0 DRAM Rank Boundary Address 0........ 154

5.2.30

EPC0DRB1—EP Channel 0 DRAM Rank Boundary Address 1 ......... 154

5.2.31

EPC0DRB2—EP Channel 0 DRAM Rank Boundary Address 2 ......... 154

5.2.32

EPC0DRB3—EP Channel 0 DRAM Rank Boundary Address 3 ......... 155

5.2.33

EPC0DRA01—EP Channel 0 DRAM Rank 0,1 Attribute.................. 155

5.2.34

EPC0DRA23—EP Channel 0 DRAM Rank 2,3 Attribute.................. 156

5.2.35

EPDCYCTRKWRTPRE—EPD CYCTRK WRT PRE............................. 156

5.2.36

EPDCYCTRKWRTACT—EPD CYCTRK WRT ACT ............................ 157

5.2.37

EPDCYCTRKWRTWR—EPD CYCTRK WRT WR .............................. 158

5.2.38

EPDCYCTRKWRTRD—EPD CYCTRK WRT READ............................ 159

5.2.39

EPDCKECONFIGREG—EPD CKE Related Configuration Register ..... 160

5.2.40

MEMEMSPACE—ME Memory Space Configuration ....................... 162

5.2.41

EPDREFCONFIG—EP DRAM Refresh Configuration....................... 163

5.2.42

TSC1—Thermal Sensor Control 1 ............................................. 165

5.2.43

TSC2—Thermal Sensor Control 2 ............................................. 166

5.2.44

TSS—Thermal Sensor Status................................................... 168

5.2.45

TSTTP—Thermal Sensor Temperature Trip Point......................... 169

5.2.46

TCO—Thermal Calibration Offset.............................................. 170

5.2.47

THERM1—Hardware Throttle Control ........................................ 171

5.2.48

TIS—Thermal Interrupt Status ................................................ 172

5.2.49

TSMICMD—Thermal SMI Command.......................................... 174

5.2.50

PMSTS—Power Management Status ......................................... 175

5.3

EPBAR .............................................................................................. 176

5.3.1

EPESD—EP Element Self Description ........................................ 176

5.3.2

EPLE1D—EP Link Entry 1 Description........................................ 177

5.3.3

EPLE1A—EP Link Entry 1 Address ............................................ 177

5.3.4

EPLE2D—EP Link Entry 2 Description........................................ 178

5.3.5

EPLE2A—EP Link Entry 2 Address ............................................ 179

PCI Express* Registers (D1:F0) ...................................................................... 180

6.1

PCI Express* Configuration Register Details (D1:F0) ............................... 183

6.1.1

VID1—Vendor Identification .................................................... 183

6.1.2

DID1—Device Identification .................................................... 183

6.1.3

PCICMD1—PCI Command ....................................................... 184

6.1.4

PCISTS1—PCI Status ............................................................. 186

6.1.5

RID1—Revision Identification .................................................. 187

6.1.6

CC1—Class Code ................................................................... 187

6.1.7

CL1—Cache Line Size............................................................. 188

6.1.8

HDR1—Header Type .............................................................. 188

6.1.9

PBUSN1—Primary Bus Number................................................ 188

6.1.10

SBUSN1—Secondary Bus Number............................................ 189

6.1.11

SUBUSN1—Subordinate Bus Number........................................ 189

6.1.12

IOBASE1—I/O Base Address ................................................... 190

6.1.13

IOLIMIT1—I/O Limit Address................................................... 190

6.1.14

SSTS1—Secondary Status ...................................................... 191

6.1.15

MBASE1—Memory Base Address.............................................. 192

6.1.16

MLIMIT1—Memory Limit Address ............................................. 193

6.1.17

PMBASE1—Prefetchable Memory Base Address .......................... 194

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