910GL datasheet(136/426 Pages) INTEL

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Host-PCI Express* Bridge Registers (D1:F0)

(Intel® 82915G/82915P/82915PL Only)

136

Datasheet

8.1.14

SSTS1—Secondary Status (D1:F0)

PCI Device:

Address Offset:

1Eh

Default Value:

00h

Access:

RO, R/W/C

Size:

16 bits

SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with

secondary side (i.e., PCI Express Graphics side) of the “virtual” PCI-PCI Bridge in the (G)MCH.

Bit

Access &

Default

Description

R/WC

Detected Parity Error (DPE):

1 = The MCH received across the link (upstream) a Posted Write Data Poisoned

TLP (EP=1).

R/WC

Received System Error (RSE):

1 = Secondary side sends an ERR_FATAL or ERR_NONFATAL message due to

an error detected by the secondary side, and the SERR Enable bit in the

Bridge Control register is 1.

R/WC

Received Master Abort (RMA):

1 = Secondary Side for Type 1 Configuration Space Header Device (for requests

initiated by the Type 1 Header Device itself) receives a completion with

Unsupported Request Completion Status.

R/WC

Received Target Abort (RTA):

1 = Secondary Side for Type 1 Configuration Space Header Device (for requests

initiated by the Type 1 Header Device itself) receives a completion with

Completer Abort Completion Status.

Signaled Target Abort (STA): Hardwired to 0. The (G)MCH does not generate

Target Aborts (the (G)MCH will never complete a request using the Completer

Abort Completion status).

10:9

00b

DEVSELB Timing (DEVT): Hardwired to 0.

R/WC

Master Data Parity Error (SMDPE).

1 = The MCH received across the link (upstream) a Read Data Completion

Poisoned TLP (EP=1).

Note: This bit can only be set when the Parity Error Enable bit in the Bridge

Control register is set.

Fast Back-to-Back (FB2B): Hardwired to 0.

Reserved

66/60 MHz capability (CAP66): Hardwired to 0.

4:0

Reserved

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