910GL datasheet(135/426 Pages) INTEL

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Host-PCI Express* Bridge Registers (D1:F0)

(Intel® 82915G/82915P/82915PL Only)

Datasheet

135

8.1.12

IOBASE1—I/O Base Address (D1:F0)

PCI Device:

Address Offset:

1Ch

Default Value:

F0h

Access:

Size:

8 bits

This register controls the processor-to-PCI Express Graphics I/O access routing based on the

following formula:

IO_BASE

≤ address ≤ IO_LIMIT

Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0]

are treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4-KB

boundary.

Bit

Access &

Default

Description

7:4

R/W

I/O Address Base (IOBASE): This field corresponds to A[15:12] of the I/O

addresses passed by bridge 1 to PCI Express*-G. BIOS must not set this register

to 00h; otherwise, 0CF8h/0CFCh accesses will be forwarded to the PCI Express

hierarchy associated with this device.

3:0

Reserved

8.1.13

IOLIMIT1—I/O Limit Address (D1:F0)

PCI Device:

Address Offset:

1Dh

Default Value:

00h

Access:

R/W

Size:

8 bits

This register controls the processor-to-PCI Express Graphics I/O access routing based on the

following formula:

IO_BASE

≤ address ≤ IO_LIMIT

Only the upper 4 bits are programmable. For the purposes of address decode, address bits A[11:0]

are assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4-

KB aligned address block.

Bit

Access &

Default

Description

7:4

R/W

I/O Address Limit (IOLIMIT): This field corresponds to A[15:12] of the I/O

address limit of device 1. Devices between this upper limit and IOBASE1 will be

passed to the PCI Express* hierarchy associated with this device.

3:0

Reserved

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