910GL datasheet(121/426 Pages) INTEL

121 / 426 page

DMIBAR Registers—Direct Media Interface (DMI) RCRB

Datasheet

121

7.1.9

DMIVC1RCTL1—DMI VC1 Resource Control

MMIO Range:

DMIBAR

Address Offset:

020h

Default Value:

00100000h

Access:

R/W, RO

Size:

32 bits

This register controls the resources associated with Virtual Channel 1.

Bit

Access &

Default

Description

R/W

Virtual Channel Enable (EN):

0 = Disable.

1 = Enable.

30:27

Reserved

26:24

R/W

001b

Virtual Channel Identifier (ID): This field indicates the ID to use for this virtual

channel.

23:20

Reserved

19:17

R/W

Port Arbitration Select (PAS): This field indicates which port table is being

programmed. The only permissible value of this field is 4h for the time-based

WRR entries.

16:8

Reserved

7:1

R/W

00h

Transaction Class / Virtual Channel Map (TVM): This field indicates which

transaction classes are mapped to this virtual channel. When a bit is set, this

transaction class is mapped to the virtual channel.

Reserved

7.1.10

DMIVC1RSTS—DMI VC1 Resource Status

MMIO Range:

DMIBAR

Address Offset:

026h

Default Value:

0000h

Access:

Size:

16 bits

This register reports the Virtual Channel specific status.

Bit

Access &

Default

Description

15:2

Reserved

VC Negotiation Pending (NP):

0 = Virtual channel is Not being negotiated with ingress ports.

1 = Virtual channel is still being negotiated with ingress ports.

Reserved

910GL Datasheet(PDF) 121 Page - Intel Corporation

910GL Datasheet(HTML) 121 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL