910GL datasheet(106/426 Pages) INTEL

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MCHBAR Registers

106

Datasheet

5.1.11

C1DRB0—Channel B DRAM Rank Boundary Address 0

MMIO Range:

MCHBAR

Address Offset:

180h

Default Value:

00h

Access:

R/W

Size:

8 bits

The operation of this register is detailed in the description for register C0DRB0.

5.1.12

C1DRB1—Channel B DRAM Rank Boundary Address 1

MMIO Range:

MCHBAR

Address Offset:

181h

Default Value:

00h

Access:

R/W

Size:

8 bits

The operation of this register is detailed in the description for register C0DRB0.

5.1.13

C1DRB2—Channel B DRAM Rank Boundary Address 2

MMIO Range:

MCHBAR

Address Offset:

182h

Default Value:

00h

Access:

R/W

Size:

8 bits

The operation of this register is detailed in the description for register C0DRB0.

5.1.14

C1DRB3—Channel B DRAM Rank Boundary Address 3

MMIO Range:

MCHBAR

Address Offset:

183h

Default Value:

00h

Access:

R/W

Size:

8 bits

The operation of this register is detailed in the description for register C0DRB0.

5.1.15

C1DRA0—Channel B DRAM Rank 0,1 Attribute

MMIO Range:

MCHBAR

Address Offset:

188h

Default Value:

00h

Access:

R/W

Size:

8 bits

The operation of this register is detailed in the description for register C0DRA0.

910GL Datasheet(PDF) 106 Page - Intel Corporation

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