5000 datasheet(85/104 Pages) INTEL

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Dual-Core Intel® Xeon® Processor 5000 Series Datasheet

Features

The Enhanced HALT state must be enabled by way of the BIOS for the processor to

remain within its specifications. The Enhanced HALT state requires support for dynamic

VID transitions in the platform.

7.2.3

Stop-Grant State

When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20

bus clocks after the response phase of the processor-issued Stop Grant Acknowledge

special bus cycle. Once the STPCLK# pin has been asserted, it may only be deasserted

once the processor is in the Stop Grant state. For the Dual-Core Intel Xeon Processor

5000 series, all logical processor cores will enter the Stop-Grant state once the

STPCLK# pin is asserted. Additionally, all logical cores must be in the Stop Grant state

before the deassertion of STPCLK#.

Since the AGTL+ signal pins receive power from the front side bus, these pins should

not be driven (allowing the level to return to VTT) for minimum power drawn by the

termination resistors in this state. In addition, all other input pins on the front side bus

should be driven to the inactive state.

BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be

latched and can be serviced by software upon exit from the Stop Grant state.

Figure 7-1. Stop Clock State Machine

Enhanced HALT or HALT State

BCLK running

Snoops and interrupts allowed

Normal State

Normal execution

Enhanced HALT Snoop or HALT

Snoop State

BCLK running

Service snoops to caches

Stop Grant State

BCLK running

Snoops and interrupts allowed

Snoop

Event

Occurs

Snoop

Event

Serviced

INIT#, BINIT#, INTR, NMI, SMI#,

RESET#, FSB interrupts

STPCLK#

Asserted

STPCLK#

De-asserted

Snoop Event Occurs

Snoop Event Serviced

HALT or MWAIT Instruction and

HALT Bus Cycle Generated

Stop Grant Snoop State

BCLK running

Service snoops to caches

5000 Datasheet(PDF) 85 Page - Intel Corporation

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