ADS1230IPW datasheet(13/29 Pages) TI1

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SETTLING TIME

DATA FORMAT

DATA RATE

AbruptChangeinExternalV

DRDY/DOUT

Startof

Conversion

1stConversion;

includes

unsettledV .

2ndConversion;

settled,but

digitalfilter

unsettled.

3rdConversion;

settled,but

digitalfilter

unsettled.

4thConversion;

settled,but

digitalfilter

unsettled.

5thConversion;

anddigital

filterboth

settled.

Conversion

Time

DRDY/DOUT

LSB

MSB

DataReady

SCLK

NewDataReady

Data

ADS1230

SBAS366A – OCTOBER 2006 – REVISED JULY 2007

In certain instances, large changes in input will

The ADS1230 outputs 20 bits of data in binary two’s

require settling time. For example, an external

complement format. The least significant bit (LSB)

multiplexer in front of the ADS1230 can put large

has a weight of 0.5VREF/(2

– 1). The positive

changes in input voltage by simply switching the

full-scale input produces an output code of 7FFFFh

multiplexer input channels. Abrupt changes in the

and the negative full-scale input produces an output

input will require four data conversion cycles to settle.

code of 800000h. The output clips at these codes for

When continuously converting, five readings may be

signals exceeding full-scale. Table 4 summarizes the

necessary in order to settle the data. If the change in

ideal output codes for different input signals.

input occurs in the middle of the first conversion, four

The ADS1230 is a 20-bit ADC. After data conversion

more full conversions of the fully-settled input are

is completed, applying 20 SCLKs retrieves 20 bits of

required to get fully-settled data. Discard the first four

data (MSB first). However, if the SCLKs continue to

readings because they contain only partially-settled

be applied after 20 bits of data are retrieved, the

data. Figure 23 illustrates the settling time for the

DOUT pin outputs four 1s for the 21st through the

ADS1230 in Continuous Conversion mode.

24th SCLK, as shown in Figure 24.

Table 4. Ideal Output Code vs Input Signal(1)

The ADS1230 data rate is set by the SPEED pin, as

INPUT SIGNAL VIN

(AINP – AINN)

IDEAL OUTPUT

shown in Table 3. When SPEED is low, the data rate

is nominally 10SPS. This data rate provides the

≥ +0.5VREF/Gain

7FFFFh

lowest noise, and also has excellent rejection of both

00001h

(+0.5VREF/Gain)/(2

19 – 1)

50Hz

and

60Hz

line-cycle

interference.

For

00000h

applications requiring fast data rates, setting SPEED

FFFFFh

(–0.5VREF/Gain)/(2

19 – 1)

high selects a data rate of nominally 80SPS.

≤ –0.5VREF/Gain

80000h

Table 3. Data Rate Settings

(1)

Excludes effects of noise, INL, offset, and

gain errors.

DATA RATE

SPEED

Internal Oscillator

External

or 4.9152MHz Crystal

Oscillator

10SPS

fCLKIN / 491,520

80SPS

fCLKIN / 61,440

Figure 23. Settling Time in Continuous Conversion Mode

Figure 24. Data Retrieval Format

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