PIC18F23K22-ESLASHML datasheet(37/496 Pages) MICROCHIP

37 / 496 page

 2010 Microchip Technology Inc.

Preliminary

DS41412C-page 37

PIC18(L)F2X/4XK22

2.5.1.1

OSCTUNE Register

The HFINTOSC/MFINTOSC oscillator circuits are

factory calibrated but can be adjusted in software by

writing to the TUN<5:0> bits of the OSCTUNE register

(Register 2-3).

The default value of the TUN<5:0> is ‘000000’. The

value is a 6-bit two’s complement number.

When the OSCTUNE register is modified, the

HFINTOSC/MFINTOSC frequency will begin shifting to

the new frequency. Code execution continues during this

shift. There is no indication that the shift has occurred.

The TUN<5:0> bits in OSCTUNE do not affect the

LFINTOSC frequency. Operation of features that

depend on the LFINTOSC clock source frequency, such

as the Power-up Timer (PWRT), Watchdog Timer

(WDT),

Fail-Safe

Clock

Monitor

(FSCM)

and

peripherals, are not affected by the change in frequency.

The OSCTUNE register also implements the INTSRC

and PLLEN bits, which control certain features of the

internal oscillator block.

The INTSRC bit allows users to select which internal

oscillator provides the clock source when the

31.25 kHz frequency option is selected. This is covered

in greater detail in Section 2.2.3 “Low Frequency

Selection”.

The PLLEN bit controls the operation of the frequency

multiplier, PLL, in internal oscillator modes. For more

details about the function of the PLLEN bit, see

Section 2.6.2 “PLL in HFINTOSC Modes”

OSCTUNE: OSCILLATOR TUNING REGISTER

R/W-0

INTSRC

PLLEN(1)

TUN<5:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

INTSRC: Internal Oscillator Low-Frequency Source Select bit

1 = 31.25 kHz device clock derived from the MFINTOSC or HFINTOSC source

0 = 31.25 kHz device clock derived directly from LFINTOSC internal oscillator

bit 6

PLLEN: Frequency Multiplier 4xPLL for HFINTOSC Enable bit(1)

1 = PLL enabled for HFINTOSC (8 MHz and 16 MHz only)

0 = PLL disabled

bit 5-0

TUN<5:0>: Frequency Tuning bits – use to adjust MFINTOSC and HFINTOSC frequencies

011111 = Maximum frequency

011110 =

• • •

000001 =

000000 = Oscillator module (HFINTOSC and MFINTOSC) are running at the factory calibrated

frequency.

111111 =

• • •

100000 = Minimum frequency

Note 1:

The PLLEN bit is active only when the HFINTOSC is the primary clock source (FOSC<2:0> = 100X) and

the selected frequency is 8 MHz or 16 MHz (IRCF<2:0> = 11x). Otherwise, the PLLEN bit is unavailable

and always reads ‘0’.

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