WLCSP16 datasheet(6/38 Pages) NXP

6 / 38 page

LPC1102

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Objective data sheet

Rev. 00 — 23 June 2010

6 of 38

NXP Semiconductors

LPC1102

32-bit ARM Cortex-M0 microcontroller

Functional description

7.1 ARM Cortex-M0 processor

The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption.

7.2 On-chip flash program memory

The LPC1102 contain 32 kB of on-chip flash memory.

Remark: The LPC1102 supports In-Application Programming (IAP) and In-System

Programming (ISP). For ISP, since there is no dedicated ISP entry pin, user code is

required to invoke ISP functionality. Unprogrammed parts will automatically boot into ISP

mode.

7.3 On-chip SRAM

The LPC1102 contain 8 on-chip static RAM memory.

7.4 Memory map

The LPC1102 incorporates several distinct memory regions, shown in the following

figures. Figure 3 shows the overall map of the entire address space from the user

program viewpoint following reset. The interrupt vector area supports address remapping.

The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128

peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32

peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows

simplifying the address decoding for each peripheral.

WLCSP16 Datasheet(PDF) 6 Page - NXP Semiconductors