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MRF24J40-I/T Datasheet(PDF) 13 Page - Microchip Technology |
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MRF24J40-I/T Datasheet(HTML) 13 Page - Microchip Technology |
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13 / 156 page  © 2010 Microchip Technology Inc. Preliminary DS39776C-page 13 MRF24J40 2.14 Memory Organization Memory in the MRF24J40 is implemented as static RAM and is accessible via the SPI port. Memory is functionally divided into control registers and data buf- fers (FIFOs), as shown in Figure 2-6. Control registers provide control, status and device addressing for MRF24J40 operations. FIFOs serve as temporary buffers for data transmission, reception and security keys. Memory is accessed via two addressing methods: Short and Long. FIGURE 2-6: MEMORY MAP FOR MRF24J40 TX Beacon FIFO Control Registers Security Key FIFO RX FIFO TX Normal FIFO TX GTS1 FIFO TX GTS2 FIFO 0x000 0x07F 0x080 0x0FF 0x100 0x17F 0x180 0x1FF 0x27F 0x200 0x280 0x2BF 0x300 0x38F Long Address Short Address Memory Space 0x00 0x3F Reserved 0x2C0 0x2FF Memory Space 128 bytes 128 bytes 128 bytes 128 bytes 128 bytes 64 bytes 144 bytes 64 bytes Control Registers |
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