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CDCU2A877

SCAS827A – AUGUST 2006 – REVISED JUNE 2007

Figure 11. Dynamic Phase Offset

Figure 12. Time Delay Between OE and Clock Output (Y, Y)

A.

Place the 2200-pF capacitor close to the PLL.

B.

Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect

trace to one GND via (farthest from the PLL).

C.

Recommended bead: Fair-Rite PN 2506036017Y0 or equilvalent (0.8

Ω dc maximum, 600Ω at 100 MHz).

11

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