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Table 41. Register 0x43 — Interrupt Status Register 3 (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W

Description

[0]

PECI0

Read−only

A Logic 1 indicates that the PECI high or low limit has been exceeded by the PECI value

from PECI Client Address 0x30. This bit is cleared on a read of the status register only if the

error condition has subsided.

[1]

DATA

Read−only

A Logic 1 indicates that valid PECI data cannot be obtained for the processor and a specified

error code has been recorded.

[2]

COMM

Read−only

A Logic 1 indicates that there is a communications error (for example, invalid FCS) on the

PECI interface.

[3]

OVT

(THERM

Temp Limit)

Read−only

OVT = 1 indicates that one of the THERM overtemperature limits has been exceeded. This bit

is cleared on a read of the status register when the temperature drops below THERM − THYST.

[6:4]

RES

Read−only

Reserved.

[7]

OOL

Read−only

OOL = 1 indicates that an out−of−limit event has been latched in Interrupt Status Register 4

(0x81). This bit is a logical OR of all status bits in Interrupt Status Register 4. Software can

test this bit in isolation to determine whether any of the voltage, temperature, or fan speed

readings represented by Interrupt Status Register 4 are out−of−limit, which eliminates the

need to read Interrupt Status Register 4 during every interrupt or polling cycle.

Table 42. Voltage Limit Registers (Note 1)

R/W

Description (Note 2)

Power−On Default

0x44

R/W

+2.5 VIN low limit.

0x00

0x45

R/W

+2.5 VIN high limit.

0xFF

0x46

R/W

VCCP low limit.

0x00

0x47

R/W

VCCP high limit.

0xFF

0x48

R/W

VCC low limit.

0x00

0x49

R/W

VCC high limit.

0xFF

0x4A

R/W

+5 VIN low limit.

0x00

0x4B

R/W

+5 VIN high limit.

0xFF

0x4C

R/W

+12 VIN low limit.

0x00

0x4D

R/W

+12 VIN high limit.

0xFF

1. Setting the Configuration Register 1 (0x40) LOCK bit has no effect on these registers.

2. High limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low limits: An interrupt is generated when a value

is equal to or below its low limit (≤ comparison).

Table 43. Temperature Limit Registers (Note 1)

R/W

Description (Note 2)

Power−On Default

0x4E

R/W

Remote 1 temperature low limit.

0x81

0x4F

R/W

Remote 1 temperature high limit.

0x7F

0x50

R/W

Local temperature low limit.

0x81

0x51

R/W

Local temperature high limit.

0x7F

0x52

R/W

Remote 2 temperature low limit.

0x81

0x53

R/W

Remote 2 temperature high limit.

0x7F

1. Exceeding any of these temperature limits by 1°C causes the appropriate status bit to be set in the interrupt status register. Setting the

Configuration Register 1 (0x40) LOCK bit has no effect on these registers.

2. High limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low limits: An interrupt is generated when a value

is equal to or below its low limit (≤ comparison).

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