MPC8308CVMAFDA datasheet(27/88 Pages) FREESCALE

27 / 88 page

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

10.2.2

DC Level Requirement for SerDes Reference Clocks

The DC level requirement for the MPC8308 SerDes reference clock inputs is different depending on the

signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described

below.

•

Differential Mode

— The input amplitude of the differential clock must be between 400 mV and 1600 mV

differential peak–peak (or between 200 mV and 800 mV differential peak). In other words,

each signal wire of the differential pair must have a single-ended swing less than 800 mV and

greater than 200 mV. This requirement is the same for both external DC-coupled or

AC-coupled connection.

— For external DC-coupled connection, as described in Section 10.2.1, “SerDes Reference

Clock Receiver Characteristics,” the maximum average current requirements sets the

requirement for average voltage (common mode voltage) to be between 100 mV and 400 mV.

Figure 17 shows the SerDes reference clock input requirement for DC-coupled connection

scheme.

— For external AC-coupled connection, there is no common mode voltage requirement for the

clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver

and the SerDes reference clock receiver operate in different command mode voltages. The

SerDes reference clock receiver in this connection scheme has its common mode voltage set to

XCOREVSS. Each signal wire of the differential inputs is allowed to swing below and above

the common mode voltage (XCOREVSS). Figure 18 shows the SerDes reference clock input

requirement for AC-coupled connection scheme.

•

Single-Ended Mode

— The reference clock can also be single ended. The SD_REF_CLK input amplitude

(single-ended swing) must be between 400 mV and 800 mV peak–peak (from Vmin to Vmax)

with SD_REF_CLK either left unconnected or tied to ground.

— The SD_REF_CLK input average voltage must be between 200 and 400 mV. Figure 19 shows

the SerDes reference clock input requirement for single-ended signaling mode.

— To meet the input amplitude requirement, the reference clock inputs might need to be DC- or

AC-coupled externally. For the best noise performance, the reference of the clock could be DC-

or AC-coupled into the unused phase (SD_REF_CLK) through the same source impedance as

the clock input (SD_REF_CLK) in use.

MPC8308CVMAFDA Datasheet(PDF) 27 Page - Freescale Semiconductor, Inc