PIC16F610-ESLASHML datasheet(21/214 Pages) MICROCHIP

21 / 214 page

DS41288F-page 21

PIC16F610/616/16HV610/616

2.2.2.4

PIE1 Register

The PIE1 register contains the peripheral interrupt

enable bits, as shown in Register 2-4.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

U-0

R/W-0

U-0

R/W-0

—ADIE(1)

CCP1IE(1)

C2IE

C1IE

—TMR2IE(1)

TMR1IE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

bit 6

ADIE: A/D Converter (ADC) Interrupt Enable bit(1)

= Enables the ADC interrupt

= Disables the ADC interrupt

bit 5

CCP1IE: CCP1 Interrupt Enable bit(1)

= Enables the CCP1 interrupt

= Disables the CCP1 interrupt

bit 4

C2IE: Comparator C2 Interrupt Enable bit

= Enables the Comparator C2 interrupt

= Disables the Comparator C2 interrupt

bit 3

C1IE: Comparator C1 Interrupt Enable bit

= Enables the Comparator C1 interrupt

= Disables the Comparator C1 interrupt

bit 2

Unimplemented: Read as ‘0’

bit 1

TMR2IE: Timer2 to PR2 Match Interrupt Enable bit(1)

= Enables the Timer2 to PR2 match interrupt

= Disables the Timer2 to PR2 match interrupt

bit 0

TMR1IE: Timer1 Overflow Interrupt Enable bit

= Enables the Timer1 overflow interrupt

= Disables the Timer1 overflow interrupt

Note 1:

PIC16F616/16HV616 only. PIC16F610/16HV610 unimplemented, read as ‘0’.

PIC16F610-E/ML Datasheet(PDF) 21 Page - Microchip Technology

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