SC68C752B datasheet(21/48 Pages) NXP

No. de pieza	SC68C752B

Descripción Electrónicos	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and 68 mode 關P interface

PDF	48 Pages

Scroll/Zoom	100%

Fabricante Electrónico	NXP [NXP Semiconductors]

Página de inicio	http://www.nxp.com

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SC68C752B_4

Product data sheet

Rev. 04 — 20 January 2010

21 of 48

NXP Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Remark: Refer to the notes under Table 10 for more register access information.

7.1 Receiver Holding Register (RHR)

The receiver section consists of the Receiver Holding Register (RHR) and the Receiver

Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data

from the RX terminal. The data is converted to parallel data and moved to the RHR. The

receiver section is controlled by the line control register. If the FIFO is disabled, location

zero of the FIFO is used to store the characters.

Remark: In this case, characters are overwritten if overflow occurs.

If overflow occurs, characters are lost. The RHR also stores the error status bits

associated with each character.

7.2 Transmit Holding Register (THR)

The transmitter section consists of the Transmit Holding Register (THR) and the Transmit

Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and

shifts it into the TSR, where it is converted to serial data and moved out on the TX

terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are

lost if overflow occurs.

SC68C752B Datasheet(PDF) 21 Page - NXP Semiconductors