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P89LPC970FDH Datasheet(PDF) 55 Page - NXP Semiconductors |
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P89LPC970FDH Datasheet(HTML) 55 Page - NXP Semiconductors |
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55 / 66 page  P89LPC97X_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 27 April 2010 55 of 66 NXP Semiconductors P89LPC970/971/972 8-bit microcontroller with accelerated two-clock 80C51 core 10.1 Waveforms Fig 17. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) tCHCL tCLCX tCHCX Tcy(clk) tCLCH 002aaa907 Fig 18. Shift register mode timing 0 1 23 45 6 7 valid valid valid valid valid valid valid valid TXLXL 002aaa906 set TI set RI tXHQX tQVXH tXHDV tXHDX clock output data write to SBUF input data clear RI Fig 19. SPI master timing (CPHA = 0) TSPICYC tSPICLKH tSPICLKH tSPICLKL tSPICLKL master LSB/MSB out master MSB/LSB out tSPIDH tSPIDSU tSPIF tSPIOH tSPIDV tSPIR tSPIDV tSPIF tSPIR tSPIF tSPIR SS SPICLK (CPOL = 0) (output) 002aaa908 SPICLK (CPOL = 1) (output) MISO (input) MOSI (output) LSB/MSB in MSB/LSB in |
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