Microsemi

Analog Mixed Signal Group

11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570

Page 3

Copyright

© 2003

Rev. 1.1, 2009-02-11

LX6433

Precision Voltage Monitor

TM

®

SIMPLIFIED BLO C K DIAGR A M

VMON

GND

+

-

REF

CLOCK

1.6MHz

Divide by

VIN

OUTPUT

RESET

SET

Clock

Divide by

Negative Edge Detector

RESET Output

Pulse Qualifier

Figure 2 –

Simplified Block Diagram

5V

1V

0V

VIN

VMON

RESET

5V

3V

0V

1.5V

1.0V

0.5V

0.0V

“THRESHOLD”

T0

T1

T2

T3

T5 T6 T7

T8

T9 T10 T11 T12

T13

T15

T4

T14

T16

T0: RESET invalid logic state for VIN < 2V

T1- T1 Vmonitor exceeds Threshold, at T1, RESET pulse remains low for 100ms until T2.

T3 - T4: Transient on VIN is ignored, less than 10usec duration for Vmonitor < THRESHOLD. (Same applies for *)

T5: Vmonitor drops below Threshold, remains low for > 10usec which activates RESET Low.

T6: Vmonitor rises above Threshold but previous fault at T5 has not cycled through full timeout (T 6-T7 < 50mS), RESET remains low.

T7: Vmonitor fals below Threshold, RESET remains low.

T7-T8 duration > 10uS, RESET timer restarted for 100mS timeout

T8-T9: Duration exceeds 150ms, RESET timer cycle completed, output rises

T10-T11: Vmonitor falls below Threshold for > 10uS, RESET signal goes low.

T13-T14, T15-T16 :Vmonitor is above Threshold, no limits apply for peak voltage or duration.

* * *

**

* * *

100ms

(typ.)

100ms

(typ.)

100ms

(typ.)

Figure 3 –

Timing Diagram