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VG37648041AT Datasheet(PDF) 49 Page - Vanguard International Semiconductor |
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VG37648041AT Datasheet(HTML) 49 Page - Vanguard International Semiconductor |
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49 / 86 page  Document : 1G5-0157 Rev.1 Page 49 VIS Preliminary VG37648041AT 256M:x4, x8, x16 CMOS Synchronous Dynamic RAM Dl b=Data In for column b 3 subsequent elements of Data In are applied in the programmed order following Dl b A non-interrupted burst of 4 is shown tWTR is referenced from the first positive CLK edge after the last Data In pair A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) The READ and WRITE commands are not necessarily to the same bank DON’T CARE UNDEFINED CLK# CLK COMMAND ADDRESS WRITE NOP NOP NOP READ NOP Col b Bank, Figure 23 WRITE TO READ - MIN DSS, NON-INTERRUPTING DQS Bank, Col n T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 DM DQ Dl b tDSS min tWTR CL |
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